MAX5216BGUA+T【PDF 5/17 页】IC DAC 16BIT SPI/SRL 8UMAX

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Maxim Integrated

14-/16-Bit, Low-Power, Buffered Output,

Rail-to-Rail DACs with SPI Interface

MAX5214/MAX5216

Table 1. Operating Mode Truth Table (MAX5214)

Serial Interface

The MAX5214/MAX5216 3-wire serial interface is com-

patible with MICROWIRE, SPI, QSPI, and DSP. The

interface provides three inputs: SCLK, CS, and DIN. The

chip-select input (CS) frames the serial data loading at

DIN. Following a chip-select input high-to-low transition,

the data is shifted synchronously and latched into the

input register on each falling edge of the serial-clock

input (SCLK). Each serial word is 16-bit for the MAX5214

and 24-bit for the MAX5216. The first 2 bits are the

control bits followed by 14 data bits (MSB first) for the

MAX5214 and 22 data bits (MSB first) for the MAX5216

as shown in Tables 1 and 2. The serial input register

transfers its contents to the input registers after loading

16/24 bits of data and updates the DAC output immedi-

ately after the data is received on the 16-/24-bit falling

edge of the clock. To initiate a new data transfer, drive

CS high and keep CS high for a minimum of 20ns before

the next write sequence. The SCLK can be either high or

low between CS write pulses. Figures 1 and 2 show the

timing diagram for the complete 3-wire serial interface

transmission. The MAX5216 DAC code is unipolar binary

with VOUT = (code/65,535) x VREF. The MAX5214 DAC

code is unipolar binary with VOUT = (code/16,383) x

VREF. See Tables 1 and 2.

Table 2. Operating Mode Truth Table (MAX5216)

16-BIT WORD

FUNCTION

CONTROL

BITS

DATA BITS

MSB

LSB

D15

D14

D13

D12

D11

D10

No operation

Power-down

(see Table 3)

B13

B12

B11

B10

Write through

Reserved, Do Not Use

24-BIT WORD

FUNCTION

CONTROL

BITS

DATA BITS

MSB

LSB

D23

D22

D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

D5–

No operation

Power-down

(see Table 3)

B15 B14 B13 B12 B11 B10 B9

Write through

Reserved, Do Not Use

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